1. Field of the Invention
The present invention relates to a memory system having a memory module and, in particular, relates to a memory system having, as a memory module, an unbuffered memory module with no buffer or register.
2. Description of the Related Art
In general, memory systems each comprise a memory module mounted thereon with memory devices, a memory controller for outputting information necessary for operations of the memory devices mounted on the memory module, i.e. command/address (C/A) signals, input data signals and so on, and a signal bus connecting between the memory controller and the memory module. For example, when the memory module is used as a main memory in a computer system, the memory controller is in the form of a chipset or the like and the signal bus is in the form of wirings extended on a mother board.
Among them, the memory modules are roughly classified into memory modules with registers (or memory modules with buffers) and unbuffered memory modules, The former is of the type having a command/address (C/A) register (or buffer) on a module substrate, while the latter is of the type having no C/A register or buffer on a module substrate.
In the memory module with register, a C/A signal sent from a memory controller is once received in a C/A register (or buffer), then distributed to memory devices mounted on a module substrate, respectively. On the other hand, in the unbuffered memory module, a C/A signal sent from a memory controller is directly distributed to all memory devices mounted on a module substrate. In other words, in the memory module with register, the capacitance seen from a C/A output terminal of the memory controller is only a capacitance of a C/A input terminal of the register or buffer, while, in the unbuffered memory module, capacitances of C/A input terminals of all the memory devices mounted on the module substrate are seen. In view of this, it has been generally carried out that when an stabler operation is sought, the memory system having the memory module with register is used, while, when giving weight to the cost, the unbuffered memory module with no buffer or register is used because the cost of the C/A register is not incurred.
With respect to the topology of a bus serving as a distribution path for C/A signals on the module substrate (hereinafter referred to as “internal C/A bus”), various proposals have been offered. As typical bus topologies, there have been known a topology having a one-step layer (hereinafter referred to as “single T-branch topology”), and a topology having two-step layers (hereinafter referred to as “dual T-branch topology”). In general, when the number of the mounted devices is large, the dual T-branch topology is better than the single T-branch topology in that inasmuch as the dual T-branch topology is approximate to equal-length wiring, differences in signal propagation delay amount on the internal C/A bus for the respective devices can be reduced as compared with the single T-branch topology being unequal-length wiring.
In recent years, improvement in data transfer rate has been strongly demanded in the field of memory devices and, following it, it is necessary to increase frequencies of C/A signals. Naturally, there has also been a demand for prices as low as possible upon constructing memory systems adaptive to high frequencies.
When considering the aspect of the low prices, the unbuffered memory module is advantageous in cost to the extent that a C/A register or buffer is not mounted on the memory module. Further, when the unbuffered memory module is adopted, it is not necessary to provide a region for mounting the C/A register or buffer therein, and thus the size of a module substrate can be reduced, thereby to excel in low height configuration.
On the other hand, if only the adaptation to the increasing frequencies of the C/A signals is considered, it is advantageous to employ the memory module with register as has been generally considered. In the memory system employing the unbuffered memory module, various problems that have not been expected may occur, such as a problem that when the frequency of a C/A signal is increased, a satisfactory waveform (i.e. waveform representing that a signal is inputted into respective memories simultaneously) can not be obtained.
Particularly, various standards are regulated with respect to the sizes of module substrates, meaning that a certain kind of limitation is imposed on the practicable module substrate sizes. This makes it difficult to adopt the equal-length wiring that is theoretically considered to be advantageous. Specifically, as a recent tendency, the number of memory devices mounted on one memory module has been increasing from various reasons, for example, for satisfying a demand for increasing the capacity of main memories following enlargement of program sizes of application software, and for increasing the data amount that can be handled at one time. However, as the number of the memory devices increases, it has been becoming difficult to realize a layout based on the equal-length wiring within a limited area. Particularly, it is difficult to ensure the balance of the wiring layout in a memory module with ECC (Error Check and Correct) function.
Suppressing unnecessary signal reflection using a terminating resistance or the like is effective means in view of waveform characteristics. On the other hand, there is also a demerit that the power consumption increases correspondingly to the electric power necessary for an operation of the terminating resistance or the like. For responding to various demands on the side of users, it is necessary to understand merits and demerits of them and offer various options.